In my prior U.S. Pat. No. 4,058,683, issued Nov. 15, 1977, I have disclosed and claimed an expandable memory for use in a telecommunication system in which the bits of lower-order frames, converging at a transmitting terminal, are assembled in interleaved relationship into a higher-order frame to be sent via a PCM link to a receiving terminal for redistribution to respective destinations. In order to harmonize the bit cadence of the higher-order frame, which also contains ancillary bits not present in the constituent lower-order frames, with the bit rates of the latter frames even though the higher bit rate is not an exact multiple of the lower one, stuffing bits are inserted from time to time into the constituent bit streams in lieu of message bits otherwise present therein, the stuffing bits being subsequently eliminated at the receiving end. The presence of a stuffing bit is marked by one or more discriminating bits preceding it in the higher-order frame, preferably three such bits whose binary value can be detected by majority logic to guard against transmission errors.
The transmitting terminal of the system referred to includes a number of expandable memories equal to the number of constituent bit streams (four in the embodiment specifically disclosed) which serve for the selective insertion of a stuffing bit. A like number of expandable memories are provided at the receiving terminal to facilitate the suppression of the stuffing and ancillary bits introduced at the transmitting terminal.
In such a system, the several output leads of a demultiplexer provided at the receiving terminal are representative of a variety of sources of binary signals having a predetermined average bit cadence subject to random variations. If it is desired to retransmit these several bit streams to their individual destinations with a substantially constant bit rate, the incoming bits will have to be stored in a buffer register from which they are read out at a rate equalling the average rate at which they are received. This calls for an expandable memory which, aside from having means for suppressing unwanted bits (as shown in my prior patent), also includes a local pulse generator whose operating frequency adjusts itself automatically to the instantaneous mean cadence of the incoming bits; by "instantaneous mean cadence" is meant the bit rate averaged over a relatively short period, such as the duration of a frame in the aforedescribed telecommunication system, as distinct from the average cadence measured over a large number of successive frame periods during which the number of message bits is subject to change by the insertion of a stuffing bit.